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d a t a sh eet preliminary speci?cation file under integrated circuits, ic11 1997 apr 08 integrated circuits tda5155 pre-amplifier for hard disk drive (hdd) with mr-read/inductive write heads
1997 apr 08 2 philips semiconductors preliminary speci?cation pre-ampli?er for hard disk drive (hdd) with mr-read/inductive write heads tda5155 contents 1 features 2 applications 3 general description 4 ordering information 5 quick reference data 6 block diagram 7 pinning 8 functional description 8.1 read mode 8.2 write mode 8.3 sleep mode 8.4 standby mode 8.5 active mode 8.6 bi-directional serial interface 8.6.1 addressing 8.6.2 programming data 8.6.3 reading data 8.7 operation of the serial interface 8.7.1 configuration 8.7.2 power control 8.7.3 head select 8.7.4 servo write 8.7.5 test 8.7.6 write amplifier programmable capacitors 8.7.7 high frequency gain attenuator register 8.7.8 high frequency gain boost register 8.7.9 settle pulse 8.7.10 address registers summary 8.8 head unsafe 8.9 hus survey 9 limiting values 10 handling 11 thermal resistance 12 recommended operation conditions 13 characteristics 14 definitions 15 life support applications
1997 apr 08 3 philips semiconductors preliminary speci?cation pre-ampli?er for hard disk drive (hdd) with mr-read/inductive write heads tda5155 1 features designed for 10 dual-stripe mr-read/inductive write heads current bias-current sense architecture single supply voltage (5.0 v 10%); a separate write drivers supply pin can be biased from v cc to 8 v +10% mr elements connected to ground (gnd) equal bias currents in the two mr stripes of each head on-chip ac couplings eliminate mr head dc offset 3-wire serial interface for programming programmable voltage/current mode write data input programmable high frequency zero-pole gain boost programmable write driver compensation capacitance programmable mr bias currents and write currents 1-bit programmable read gain sleep, standby, active and test modes available measurement of head resistances in test mode in test mode, one mr bias current may be forced to a minimum current short write current rise and fall times with near rail-to-rail voltage swing head unsafe pin for signalling of abnormal conditions and behaviour low supply voltage write current inhibit (active or inactive) support servo writing provide temperature monitor thermal asperity detection with programmable threshold level requires only one external resistor. 2 applications hard disk drive (hdd). 3 general description the 5.0 v pre-amplifier for hdd applications has been designed for five terminal, dual-stripe magneto-resistive (mr)-read/inductive write heads. the disks of the disk drive are connected to ground. to avoid voltage breakthrough between the heads and the disk, the mr elements of the heads are also connected to ground. the symmetry of the dual-stripe head-amplifier combination automatically distinguishes between the differential signals such as signals and the common-mode effects like interference. the latter are rejected by the amplifier. the device incorporates read amplifiers, write amplifiers, a serial interface, digital-to-analog converters, reference and control circuits which all operate on a single supply voltage of 5 v 10%. the output drivers have a separate supply voltage pin which can be connected to a higher supply voltage of up to 8 v +10%. the complementary output stages of the write amplifier allow writing with near rail-to-rail peak voltages across the inductive write head. the read amplifier has low input impedance. the dc offset between the two stripes of the mr head is eliminated using on-chip ac coupling. fast settling features are used to keep the transients short. as an option, the read amplifier may be left biased during writing so as to reduce the duration of these transients even further. series inductance in the leads between the amplifier and mr heads influences the bandwidth which can be compensated by using a programmable high frequency gain boost (hf zero). hf noise and bandwidth can be attenuated using a programmable high frequency gain attenuator (hf pole). on-chip digital-to-analog converters for mr bias currents and write currents are programmed via a 3-wire serial interface. head selection, mode control, testing and servo writing can also be programmed using the serial interface. in sleep mode the cmos serial interface is operational. fig.1 shows the block diagram of the device. 4 ordering information type number package name description version TDA5155X - naked die -
1997 apr 08 4 philips semiconductors preliminary speci?cation pre-ampli?er for hard disk drive (hdd) with mr-read/inductive write heads tda5155 5 quick reference data symbol parameter conditions min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v v cc(wd) supply voltage for write drivers v cc 8.0 8.8 v g v(dif) differential voltage gain from head inputs to rdx, rdy; r mr =28 w ; i mr =10ma data bit d4 = 0 - 160 - data bit d4 = 1 - 226 - b - 3db - 3 db frequency bandwidth upper bandwidth without gain boost (4 nh lead inductance) - 220 - mhz f noise ?gure r mr =28 w ; i mr =10ma; t amb =25 c; f = 20 mhz - 3.0 3.2 db v irn input referred noise voltage r mr =28 w ; i mr =10ma; t amb =25 c; f = 20 mhz - 0.9 1.0 nv/ ? hz cmrr common mode rejection ratio r mr mismatch <5% i mr =10ma f < 1 mhz - 45 - db f < 100 mhz - 25 - db psrr power supply rejection ratio (input referred) r mr mismatch <5% i mr =10ma f < 1 mhz - 80 - db f < 100 mhz - 50 - db t r , t f write current rise/fall time (10% to 90%) l h = 150 nh; r h =10 w; i wr = 35 ma; f = 20 mhz v cc(wd) = 8.0 v -- 1.8 ns v cc(wd) = 6.5 v -- 2.1 ns i mr(pr) programming mr bias current range r ext =10k w 5 - 20.5 ma i wr(b-p) programming write current range (base-to-peak) r ext =10k w 20 - 51 ma f sclk serial interface clock rate -- 25 mhz
1997 apr 08 5 philips semiconductors preliminary speci?cation pre-ampli?er for hard disk drive (hdd) with mr-read/inductive write heads tda5155 6 block diagram fig.1 block diagram. handbook, full pagewidth mgg982 serial interface write driver input head unsafe indicator ff voltage reference 10 3 5 4 5 6 11 20 k w 8 9 10 17 13 14 3 7 4 4 write driver and read preamp (10 ) tda5155 head select write current source low supply voltage indicator v cc(wd) (5 to 8 v) nwy nwx nry ngnd nrx gndn 2, 12, 15, 18 23, 28, 33, 38, 43, 48, 53, 58, 63, 68 22, 27, 32, 37, 42, 47, 52, 57, 62, 67 21, 26, 31, 36, 41, 46, 51, 56, 61, 66 19, 24, 29, 34, 39, 44, 49, 54, 59, 64 20, 25, 30, 35, 40, 45, 50, 55, 60, 65 10 1 v cc 16 10 10 10 10 10 rdy rdx r ext sdata sen sclk wdly(i) wdlx(i) 4 tas detector 5 wdly(v) wdlx(v) hus r/w +v cc r mr current source
1997 apr 08 6 philips semiconductors preliminary speci?cation pre-ampli?er for hard disk drive (hdd) with mr-read/inductive write heads tda5155 7 pinning symbol pad description v cc(wd) 1 supply voltage for the write drivers gnd1 2 ground connection 1 hus 3 head unsafe output wdix(v) 4 write data input (differential, voltage input) wdiy(v) 5 write data input (differential, voltage input) wdix(i) 6 write data input (differential, current input) wdiy(i) 7 write data input (differential, current input) r/ w 8 read/write (read = active high, write = active low) sen 9 serial bus enable sdata 10 serial bus data sclk 11 serial bus clock gnd2 12 ground connection 2 rdx 13 read data output (differential x - y) rdy 14 read data output (differential x - y) gnd3 15 ground connection 3 v cc 16 supply voltage r ext 17 10 k w external resistor gnd4 18 ground connection 4 0wx 19 inductive write head connection for head h0 (differential x - y) 0wy 20 inductive write head connection for head h0 (differential x - y) 0rx 21 mr-read head connection for head h0 (differential x - y) 0gnd 22 ground connection for head h0 0ry 23 mr-read head connection for head h0 (differential x - y) 1wx 24 inductive write head connection for head h1 (differential x - y) 1wy 25 inductive write head connection for head h1 (differential x - y) 1rx 26 mr-read head connection for head h1 (differential x - y) 1gnd 27 ground connection for head h1 1ry 28 mr-read head connection for head h1 (differential x - y) 2wx 29 inductive write head connection for head h2 (differential x - y) 2wy 30 inductive write head connection for head h2 (differential x - y) 2rx 31 mr-read head connection for head h2 (differential x - y) 2gnd 32 ground connection for head h2 2ry 33 mr-read head connection for head h2 (differential x - y) 3wx 34 inductive write head connection for head h3 (differential x - y) 3wy 35 inductive write head connection for head h3 (differential x - y) 3rx 36 mr-read head connection for head h3 (differential x - y) 3gnd 37 ground connection for head h3 3ry 38 mr-read head connection for head h3 (differential x - y) 4wx 39 inductive write head connection for head h4 (differential x - y) 4wy 40 inductive write head connection for head h4 (differential x - y) 4rx 41 mr-read head connection for head h4 (differential x - y) 4gnd 42 ground connection for head h4 4ry 43 mr-read head connection for head h4 (differential x - y) 5wx 44 inductive write head connection for head h5 (differential x - y) 5wy 45 inductive write head connection for head h5 (differential x - y) 5rx 46 mr-read head connection for head h5 (differential x - y) 5gnd 47 ground connection for head h5 5ry 48 mr-read head connection for head h5 (differential x - y) 6wx 49 inductive write head connection for head h6 (differential x - y) 6wy 50 inductive write head connection for head h6 (differential x - y) 6rx 51 mr-read head connection for head h6 (differential x - y) 6gnd 52 ground connection for head h6 6ry 53 mr-read head connection for head h6 (differential x - y) 7wx 54 inductive write head connection for head h7 (differential x - y) symbol pad description
1997 apr 08 7 philips semiconductors preliminary speci?cation pre-ampli?er for hard disk drive (hdd) with mr-read/inductive write heads tda5155 7wy 55 inductive write head connection for head h7 (differential x - y) 7rx 56 mr-read head connection for head h7 (differential x - y) 7gnd 57 ground connection for head h7 7ry 58 mr-read head connection for head h7 (differential x - y) 8wx 59 inductive write head connection for head h8 (differential x - y) 8wy 60 inductive write head connection for head h8 (differential x - y) 8rx 61 mr-read head connection for head h8 (differential x - y) symbol pad description 8gnd 62 ground connection for head h8 8ry 63 mr-read head connection for head h8 (differential x - y) 9wx 64 inductive write head connection for head h9 (differential x - y) 9wy 65 inductive write head connection for head h9 (differential x - y) 9rx 66 mr-read head connection for head h9 (differential x - y) 9gnd 67 ground connection for head h9 9ry 68 mr-read head connection for head h9 (differential x - y) symbol pad description fig.2 pad arrangement. handbook, full pagewidth mgg981 v cc(wd) wdix(v) wdiy(v) wdix(i) wdiy(i) sclk sdata sen v cc r ext gnd3 gnd4 gnd2 0 r/w 18 3wx 3wy 3rx 3gnd 3ry 4wx 4wy 4rx 4gnd 2ry 2gnd 2rx 2wy 2wx 1ry 1gnd 1rx 1wy 1wx 0ry 0gnd 0rx 0wy 0wx 4ry 5wx 5wy 5rx 5gnd 5ry 6wx 6wy 6rx 6ry 7wx 7wy 7rx 7gnd 7ry 8wx 8wy 8rx 8gnd 9wx 9wy 9ry 9rx 9gnd 8ry 34 35 36 37 38 39 40 41 42 43 45 47 49 51 53 6gnd 44 46 48 50 52 64 65 66 67 68 54 55 56 57 58 59 60 61 62 63 16 rdx rdy 17 15 13 11 14 12 10 9 8 7 6 5 4 3 1 gnd1 hus 2 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 tda5155
1997 apr 08 8 philips semiconductors preliminary speci?cation pre-ampli?er for hard disk drive (hdd) with mr-read/inductive write heads tda5155 8 functional description 8.1 read mode the read mode disables the write circuitry to save power while reading. the read circuitry is disactivated for write, sleep and standby modes. the read circuitry may also be biased during write mode to shorten transients. the selected head is connected to a multiplexed low-noise read amplifier. the read amplifier has low-impedance inputs nrx and nry (n is the number of the head) and low-impedance outputs rdx and rdy. the signal polarity is non-inverting from x and y inputs to x and y outputs. ambient magnetic fields at the mr elements result in a relative change in mr resistance: this change produces a current variation: , where i mr is the bias current in the mr element. the current variation is amplified to form the read data output signal voltage, which is available at rdx and rdy. ac coupling between mr elements and amplifier stages prevents the amplifier input stages from overloading by dc voltages across the mr elements. a fast settling procedure shortens dc settling transients. an on-chip generated stable temperature reference voltage (1.32 v), available at the r ext pin, is dropped across an external resistor (10 k w ) to form a global reference current for the write and the mr bias currents. the mr bias current dacs are programmed through the serial interface according to the following formula: (in ma), where d4-d0 are bits (either logic 0 or logic 1). at power-up all bits are set to logic 0, which results in a default mr current of 5 ma. the adjustable range of the mr currents is 5 ma to 20.5 ma. the mr bias currents are equal for the two stripes of each head. the gain amplifier is 1-bit programmable. the amplifier gain can be set to its nominal value or to the nominal value +3 db. dr mr r mr -------------- di mr i mr dr mr r mr -------------- = i mr 0.5 10k w r ext -------------- - 10 16d4 8d3 4d2 2d1 d0 +++++ () = 8.2 write mode to minimize power dissipation, the read circuitry may be disabled in write mode. the write circuitry is disabled in read, sleep and standby modes. in write mode, a programmable current is forced through the selected two-terminal inductive write head. the push-pull output drivers yield near rail-to-rail voltage swings for fast current polarity switching. the write data input can be either voltage or current input (see chapter 12). in voltage mode, the differential write data inputs wdix(v) and wdiy(v) are pecl (positive emitter coupled logic) compatible. the write data flip-flop can either be used or passed-by. in the case that the write data flip-flop is used, current polarity is toggled at the falling edges of switching to write mode initializes the data flip-flop so that the write current flows in the write head from x to y. in the case that the write data flip-flop is not used, the signal polarity is non-inverting from x and y inputs to x and y outputs. the write current magnitude is controlled through on-chip dacs. the write current is defined as follows: (in ma), where d4-d0 are bits (either logic 0 or logic 1). the adjustable range of the write current is 20 ma to 51 ma. at power-up, the default values d4 = d3 = d2 = d1 = d0 = logic 0 are initialized, corresponding to i wr = 20 ma. i wr is the current provided by the write drivers: the current in the write coil and in the damping resistor together. the static current in the write coil is , where r h is the resistance of the coil including leads and r d is the damping resistor. v data v wdix v () v wdiy v () C 2 ----------------------------------------------------- - = i wr 10k w r ext -------------- - 20 16d4 8d3 4d2 2d1 d0 +++++ () = i wr 1 r h r d ------ - + ---------------- -
1997 apr 08 9 philips semiconductors preliminary speci?cation pre-ampli?er for hard disk drive (hdd) with mr-read/inductive write heads tda5155 8.3 sleep mode in sleep mode, the device is accessible via the serial interface. all circuits are inactive, except the circuits of the cmos serial interface and the circuitry which forces the data registers to their default values at power-up and which fixes the dc level of outputs rdx and rdy (required when operating with more than one amplifier). typical static current consumption is - 30 m a. dynamic current consumption during operation of the serial interface in sleep mode due to external activity at the inputs to the serial interface is not included. in all modes, including the sleep mode, data registers can be programmed. sleep is the default mode at power-up. switching to other modes takes less than 0.1 ms. 8.4 standby mode the circuit can be put in standby mode using the serial interface. in standby mode, the typical dc current consumption is 330 m a. transients from standby mode to active mode are two orders of magnitude shorter than from sleep mode to active mode. this is important in the case of cylinder mode operation with multiple amplifiers. all amplifiers can operate from standby mode and all head switch times can be kept just as short as in the case of operation with a single amplifier. head switch times are summarized in the switching characteristics. 8.5 active mode active mode is either read mode or write mode depending on the status of the r/ w pin. 8.6 bi-directional serial interface the serial interface is used for programming the device and for reading of status information. 16 bits (8 bits for data and 8 for address) are used to program the device. the serial interface requires 3 pins: sdata, sclk and sen. these pins (and r/ w as well) are cmos inputs. the logic input r/ w has an internal 20 k w pull-up resistor and the sen logic input has an internal 20 k w pull-down resistor. thus, in case the sen line is opened, no data will be registered and in case the r/ w line is opened, the device will never be in write mode. sdata: serial data; bi-directional data interface. in all circumstances, the lsb is transmitted first . sclk: serial clock; 25 mhz clock frequency. sen: serial enable; data transfer takes place when sen is high. when sen is low, data and clock signals are prohibited from entering the circuit. three phases in the communication are distinguishable: addressing, programming and reading. each communication sequence starts with an addressing phase, followed by either a programming phase or a reading phase. 8.6.1 a ddressing when sen goes high, bits are latched in at rising edges of sclk. the first eight bits a7 to a0 (starting with a0) are shifted serially into an address register. if sen goes low before 16 bits have been received, the operation is ignored. when more than 16 bits (address and data) are latched in before sen goes low, the first 8 bits are interpreted as an address and the last 8 bits as data. sen should go high at least 5 ns before the first rising edge of sclk. data should be valid at least 5 ns before and after a rising edge of sclk. the first six bits a5 to a0 constitute the register address. bit a6 is unused. if bit a7 = logic 0, a programming sequence starts. if bit a7 = logic 1, reading data from the pre-amplifier can start. 8.6.2 p rogramming data if a7 = 0, the last eight bits d7 to d0 before sen goes low are shifted into an input register. when sen goes low, the communication sequence is ended and the data in the input register is copied in parallel to the data register that corresponds to the decoded address a0 to a5. sen should go low at least 5 ns after the last rising edge of sclk. see fig.3 for the timing diagram of the programming. 8.6.3 r eading data immediately after the ic detects that a7 = logic 1, data from the data register (address a5 to a0) is copied in parallel to the input register. two wait clock cycles must follow before the controller can start inputting data. at the first falling edge of sclk after the 2 wait rising edges of sclk, the lsb d0 is placed on sdata line followed by d1 at the next falling edge of sclk etc. if sen goes low before 8 address bits (a7 to a0) have been detected, the communication is ignored. if sen goes low before the 8 data bits have been sent out of the ic, the reading sequence is immediately interrupted. see fig.4 for the timing diagram of the reading via the serial interface.
1997 apr 08 10 philips semiconductors preliminary speci?cation pre-ampli?er for hard disk drive (hdd) with mr-read/inductive write heads tda5155 fig.3 timing diagram of the write sequence of the serial interface operation (a7 = logic 0). handbook, full pagewidth mgg983 address data a0 d0 a1 d1 a2 d2 a3 d3 a4 d4 a5 d5 a6 d6 0d7 sclk sdata sen fig.4 timing diagram of the read sequence of the serial interface operation a7 = logic 1). handbook, full pagewidth address data wait cycles a0 d0 a1 d1 a2 d2 a3 d3 a4 d4 a5 d5 a6 d6 1d7 sclk sdata sen mgg984
1997 apr 08 11 philips semiconductors preliminary speci?cation pre-ampli?er for hard disk drive (hdd) with mr-read/inductive write heads tda5155 8.7 operation of the serial interface the serial interface programming is summarized in section 8.7.10. 8.7.1 c onfiguration d0: by default (d0 = logic 0), write data passes from the write data input via the data flip-flop to the write driver. the write driver toggles the current in the head at the falling edges of: or when d0 = logic 1, the write data flip-flop is not used. the signal polarity is non-inverting from the inputs wdix and wdiy to the outputs nwx and nwy. d1: by default (d1 = logic 0), the pre-amplifier senses pecl write signals at wdix(v) and wdiy(v). when d1 = logic 1, the pre-amplifier senses input write currents at wdix(i) and wdiy(i). d2: by default (d2 = logic 0), the write current is inhibited under low supply voltage conditions. the write current inhibit is made inactive by programming d2 to logic 1. d3: by default (d3 = logic 0), in write mode low supply voltage, open head, and other conditions are monitored and flagged at hus. if d3 = logic 1, hus is low in write mode and high in read mode. d4: the amplifier read gain may be programmed in the configuration register. by default (d4 = logic 0), the read gain is typically 160 with r mr =28 w . if d4 = logic 1, the read amplifier gain is 3 db higher (226 in this case). d5: in order to minimize the write-to-read recovery times, the first stage of the read amplifier may be kept biased during write mode. by default, (d5 = logic 0) the read amplifier is powered down during write mode, and the fast settling procedure is activated after write-to-read switching. if d5 = logic 1 the read amplifier is kept biased during write mode, and the fast settling procedure still occurs if the head is changed or the mr current is re-programmed. v data v wdix v () v wdiy v () C 2 ----------------------------------------------------- - = i data i wdix i () i wdiy i () C 2 ---------------------------------------------- = 8.7.2 p ower control by default, d1 = d0 = logic 0, the pre-amplifier powers up in sleep mode. if d1 = logic 0, d0 = logic 1 or d1 = logic 1, d0 = logic 0 the circuit goes in standby mode. if d1 = d0 = logic 1, the circuit goes in active mode (read or write mode depending on the r/ w input). 8.7.3 h ead select selection of a wrong head (h10-h15) causes an head unsafe condition. hus goes high when in write mode a wrong head is selected and when d3 in the configuration register is low. when in read mode and a wrong head is selected, head h0 is therefore selected and if d3 in the configuration register is low, hus goes low. 8.7.4 s ervo write the circuit is prepared for servo writing. however, the device will not be guaranteed. 8.7.5 t est d2 = d1 = d0 = logic 0. the circuit is not in test mode. this is the default situation. 8.7.5.1 mr head test d2 = logic 0, d1 = logic 0, d0 = logic 1. in read mode, the voltages at rx and ry (at the top of the mr elements) of the selected head are fed to outputs rdx and rdy. by measuring the output voltages single ended at two different i mr currents, the mr resistance can be accurately measured according to the following formula: for the x-side. open head and head short-circuited-to-ground conditions can therefore be detected. d2 = logic 0, d1 = logic 1, d0 = logic 0. same as before, with the difference that i mr2 is fixed to a minimum constant value of 5 ma. measuring in the same way as above with i mr1 > 5 ma, enables the detection of mr elements shorted together. 8.7.5.2 temperature monitor d2 = logic 0, d1 = logic 1, d0 = logic 1. the temperature monitor voltages are connected to rdx and rdy. the output differential voltage depends on the temperature according to: dv = - 0.00364 t + 1.7; 0 < t < 140 c. the temperature may be measured with a typical precision of 5 c. r mrx v rdx1 v rdx2 C i mrx1 i mrx2 C -------------------------------------- - =
1997 apr 08 12 philips semiconductors preliminary speci?cation pre-ampli?er for hard disk drive (hdd) with mr-read/inductive write heads tda5155 8.7.5.3 thermal asperity detector d2 = logic 1, d1 = x, d0 = (0,1). unlike the above tests, the thermal asperity detection does not use the rdx and rdy outputs. thus, the reader is fully operational. in case a thermal asperity is detected, it is flagged at the hus pin. the threshold voltage for the thermal asperity detection is 2-bit programmable. these 2 bits consist of d0 (lsb) of the test mode register (address = 0xxx0110), and d2 of the compensation capacitor register (address = 0xxx0111). d0 of test mode register; d2 of the compensation capacitor register. 8.7.6 w rite amplifier programmable capacitors by default (d2 = d1 = d0 = logic 0) the programmable capacitors are zero. these capacitors are used to improve the performance of the write amplifier according to the write amplifier output load. 8.7.7 h igh frequency gain attenuator register by default (d3 = d2 = d1 = d0 = logic 0) the high frequency gain attenuator is not active. the gain attenuator provides a pole which limits the bandwidth and reduces the high v th 210 560.d0 280.d2 ++ ()m v = frequency noise. the hf pole can be used in combination with the hf zero in order to boost the hf gain locally and yet limit the very high frequency noise enhancement. 8.7.8 h igh frequency gain boost register by default (d3 = d2 = d1 = d0 = logic 0) the high frequency gain boost is not active. the gain boost provides a zero which allows to optimize the bandwidth of the read amplifier and to correct for attenuation caused by series inductances in the leads between the mr heads and the read amplifier inputs. 8.7.9 s ettle pulse by default (d2 = d1 = d0 = logic 0) the settle pulse has a nominal duration of 3 m s. its value can be programmed from 2.125 m s to 3 m s according to the following formula: the settle pulse is used to shorten the transients during switching. t st 2 m s 1 4.d2 2.d1 1.d0 1 +++ () ------------------------------------------------------------------ - m s + = 8.7.10 a ddress registers summary address registers (1) function a7 a6 a5 a4 a3 a2 a1 a0 0xxx0000 configuration register: d0 = 0: use data flip-flop; d0 = 1: by-pass data flip-flop d1 = 0: wdi pecl; d1 = 1: current input d2 = 0: write current inhibit active; d2 = 1: write current inhibit inactive read mode: d3 = 0: hus active; d3 = 1: hus high write mode: d3 = 0: hus active; d3 = 1: hus low d4 = 0: read gain nominal; d3 = 1: read gain +3 db d5 = 0: read amplifier off during write mode; d5 = 1: read amplifier on during write mode 0xxx0001 power control register: (d1,d0) = (0,0): sleep mode (d1,d0) = (1,0) or (0,1): standby mode (d1,d0) = (1,1): active mode (write or read) 0xxx0010 head select register: (d3,d2,d1,d0) = (0,0,0,0) to (1,0,0,1): h0 to h9 addressing h10 to h15 causes hus to go high if in write mode and h0 to be selected if in read mode
1997 apr 08 13 philips semiconductors preliminary speci?cation pre-ampli?er for hard disk drive (hdd) with mr-read/inductive write heads tda5155 notes 1. unused bits in the registers (indicated by x) are dont care. default data, initialized at power-up, is zero in all registers. for v cc <2.5 v, the register contents are not guaranteed. 2. v th programming uses both the test mode register and the compensation capacitor register. d0 in the formula above is the lsb of the test mode register and d2 is the d2 data bit of the compensation capacitor register. 0xxx0011 mr current dac register: ma 0xxx0100 write current dac register: ma 0xxx0101 servo write register: (d0,d1) = (0,0): one head (d0,d1) = (1,1): all heads (d0,d1) = (1,0): odd numbered heads (h1, h3, h5, h7 and h9) (d0,d1) = (0,1): even numbered heads (h0, h2, h4, h6 and h8) 0xxx0110 test mode register: (d2,d1,d0) = (0,0,0) = not in test mode (d2,d1,d0) = (0,0,1) = read head test (i mr1 =i mr2 ) (d2,d1,d0) = (0,1,0) = read head test (i mr2 = 5 ma fixed) (d2,d1,d0) = (0,1,1) = temperature monitor (d2,d1,d0) = (1,x,d0) = thermal asperity detection, see note 2 v th = (210 + 560.d0 + 280.d2) m v 0xxx0111 compensation capacitor register: equivalent differential capacitance = (4.d2 + 2.d1 + 1.d0) 2pf 0xxx1000 high frequency gain attenuator register nominal pole frequency = 0xxx1001 high frequency gain boost register nominal zero frequency = 0xxx1010 settle time register settle time: 1xxx1111 device id register id = 8.d3 + 4.d2 + 2.d1 + 1.d0; d3 to d0 are preset to (0,0,1,1) 1 xxxa3a2a1a0 when a7 = 1, data from the register with address a3 to a0 is read out on sdata address registers (1) function a7 a6 a5 a4 a3 a2 a1 a0 i mr 0.5 10k w r ext -------------- - 10 16.d4 8.d3 4.d2 2.d1 d0 + ++++ () = i wr 10k w r ext -------------- - 20 16.d4 8.d3 4.d2 2.d1 d0 + ++++ () = 800 mhz 8.d3 4.d2 2.d1 1.d0 +++ --------------------------------------------------------------------- 800 mhz 8.d3 4.d2 2.d1 1.d0 +++ --------------------------------------------------------------------- t st 2 m s 1 4.d2 2.d1 1.d0 1 +++ () ------------------------------------------------------------------ - m s + =
1997 apr 08 14 philips semiconductors preliminary speci?cation pre-ampli?er for hard disk drive (hdd) with mr-read/inductive write heads tda5155 8.8 head unsafe the hus pin is an open collector output. therefore when the pin is not connected to an external pull-up resistor, hus is low. hus pins can be connected together in case of operation with more than one amplifier. it is used to detect abnormal or unexpected operation. sleep mode: hus is high, to permit working with more than one amplifier. standby mode: hus is high, to permit working with more than one amplifier. read mode: if in the configuration register d3 = 1, hus is high if in the configuration register d3 = 0, hus goes low for: C selection of a wrong head (h10 to h15) (1) Cr ext pin open, short-circuited to ground or to v cc (read current too low or too high) C low v cc and v cc(wd) conditions. a low supply voltage detector is placed close to the v cc and v cc(wd) pins. detection of low v cc (main supply): a v cc supply voltage below 4.0 v 5% is flagged at the hus pin. the voltage detection range is then 4.2 to 3.8 v with an hysteresis of 110 mv 10%. detection of low v cc(wd) (write drivers supply): a fault will be flagged at the hus pin if v cc(wd) drops 0.8 v 10% below v cc . one must be aware that such a detection is only aimed to warn for a catastrophic situation. indeed, v cc(wd) should never be below v cc . test mode: hus is high except when the tas detector is on. if a thermal asperity is detected, hus goes low. servo write mode: hus is low. write mode: if in the configuration register d3 = 1, hus is low if in the configuration register d3 = 0, hus goes high for: C selection of a wrong head (h10 to h15) (1) Cr ext pin open, short-circuited to ground or to v cc (write current too low or too high) C write data input frequency too low (wdix-wdiy) C write head wx, wy open, wx or wy short-circuited to ground (2) C write driver still left biased while not selected C low v cc and v cc(wd) conditions (write current inhibit can be active or inactive). the same detector is used for read and write mode. the write current may be inhibited if d2 = 0 in the configuration register. the hus line indicates an unsafe condition as long as the fault is present, in read mode as well as in write mode. it indicates again a safe condition only 0.5 m s to 1 m s after the last fault has disappeared. (1) head numbers 0 to 9 are correct, 10 to 15 are signalled as unsafe. (2) switching to write mode makes hus low. after the transient the hus detection circuitry is activated. the target for the head open detection time is 15 ns. 8.9 hus survey notes 1. a-test mode = analog test mode. 2. in servo mode, the performance of the ic is not guaranteed. hus data bit d3 mode state 0 1 sleep mode -- high high standby mode -- high high active mode read read mode active high a-test mode (1) high high tas mode active active write write mode active low a-test mode (1) high high servo mode (2) low low
1997 apr 08 15 philips semiconductors preliminary speci?cation pre-ampli?er for hard disk drive (hdd) with mr-read/inductive write heads tda5155 9 limiting values in accordance with the absolute maximum rating system (iec 134). 10 handling inputs and outputs are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. 11 thermal characteristics the thermal resistance depends on the flex used. the TDA5155X is shipped in naked dies form. symbol parameter min. max. unit v cc supply voltage - 0.5 +6.0 v v cc(wd) write driver supply voltage - 0.5 +9.5 v v n1 voltage on all pins except v cc(wd) , read inputs nrx, nry and write driver outputs nwx, nwy (n = 0 to 9) - 0.5 +5.5 v absolute maximum value - v cc + 0.5 v v n2 voltage on write driver outputs nwx, nwy - 0.5 +8.8 v absolute maximum value - v cc(wd) + 0.5 v v n3 voltage on read inputs nrx, nry - 0.5 +1 v i ngnd ground current (pins ngnd) - 0.1 a t stg storage temperature - 65 +150 c t j junction temperature - 150 c
1997 apr 08 16 philips semiconductors preliminary speci?cation pre-ampli?er for hard disk drive (hdd) with mr-read/inductive write heads tda5155 12 recommended operation conditions symbol parameter conditions min. typ max. unit v cc supply voltage note 1 4.5 - 5.5 v v cc(wd) write driver supply voltage note 2 v cc - 8.8 v v ih high level input voltage (cmos) 3.5 - v cc v v il low level input voltage (cmos) 0 - 0.8 v v i(dif)(p-p) differential input voltage (peak-to-peak value) note 3 0.4 0.7 1.5 v v ih(pecl) high level pecl input voltage note 3 - 2.85 v cc v v il(pecl) low level pecl input voltage note 3 1.5 2.15 - v i i(dif)(p-p) differential input current (peak-to-peak value) note 4 0.4 0.8 1.0 ma i ih(dif) high level differential input current note 4 - 1.4 - 1.2 - ma i il(dif) low level differential input current note 4 - - 0.4 - 0.1 ma t amb ambient temperature 0 - 70 c t j junction temperature reading -- 110 c writing (v cc(wd) =8v) -- 130 c r mr mr element resistance 15 28 34 w d (r mr )r mr mismatch note 5 -- 4 w l l(tot) total lead inductance to the head in each lead; note 6 - 25 - nh r l(tot) total lead resistance to the head in each lead; note 6 - 1.5 - w v mr voltage on top of mr elements note 7 -- 0.5 v v sig(dif)(p-p) differential mr head input voltage (peak-to-peak value) 0.4 1 2 mv l wh write head inductance including lead; note 6 - 0.15 - m h r wh write head resistance including lead; note 6 - 10 - w c wh write head capacitance including lead; note 6 - tbf - pf r ext external reference resistor - 10 - k w i ref v ref r ext ---------- - =
1997 apr 08 17 philips semiconductors preliminary speci?cation pre-ampli?er for hard disk drive (hdd) with mr-read/inductive write heads tda5155 notes to the recommended operating conditions 1. a supply by-pass capacitor from v cc to ground or a low pass filter may be used to optimize the psrr. 2. the supply voltage v cc(wd) must never be below v cc in normal mode, and two diode 1.4 v above v cc in servo mode. 3. the given values should be interpreted in the way that the single ended voltage could swing from 0.2 to 0.75 v, and that the common mode voltage should be such that for any of the two states, the v ih(pecl) is less than v cc and v il(pecl) is more than 1.5 v. pecl voltage swing: a wider peak-to-peak voltage swing can be used. in that case a current will flow through the wdi inputs. this current is approximately equal to wdix v () wdiy v () C 1.4 C 200 ------------------------------------------------------------------------ - 4. same comments for the given values as for the voltage input mode. the high (respectively low) level input current is defined such that it produces the same effect at the output of the writer (wx, wy) as the high (resp. low) level input voltage. 5. the mismatch refers to the resistance of the two stripes of the same head. this is defined as follows: d (r mr ) = abs(r mr1 - r mr2 ). 6. these parameters depend on the head model. the data given in the table are those used for testing. 7. the combination of maximum head resistance, lead resistance and bias current is not permitted. to avoid voltage breakthrough between heads and disk, the voltage over the mr elements is limited by two diode voltages.
1997 apr 08 18 philips semiconductors preliminary speci?cation pre-ampli?er for hard disk drive (hdd) with mr-read/inductive write heads tda5155 13 characteristics v cc = 5.0 v; v cc(wd) =8v; v gnd =0v; t amb =25 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit read characteristics i mr mr current adjust range r ext =10k w ; 0.5 ma steps 5 - 20.5 ma d i mr tolerance (excluding r ext )i mr programmed at 10 ma - 4 - % g v(dif) differential voltage gain; note 1 from head inputs to rdx, rdy; r mr =28 w ; i mr =10ma; f = 20 mhz d4 = 0 - 160 - d4 = 1 - 226 - r i(dif) differential input resistance i mr =10ma - 13 -w c i(dif) differential input capacitance - 16 - pf thd total harmonic distortion - 1 - % b l lower signal gain pass-band edge - 3db -- 100 khz b h higher signal gain pass-band edge - 3 db; note 2 without gain boost (4 nh lead inductance) - 220 - mhz with gain boost (50 nh lead inductance) - 170 - mhz f noise ?gure r mr =28 w ; i mr = 10 ma; t amb =25 c; f = 20 mhz - 3.0 3.2 db v irn input referred noise voltage; note 3 r mr =28 w ; i mr = 10 ma; t amb =25 c; f = 20 mhz - 0.9 1.0 nv/ ? hz b f(l) lower noise band edge (+3 db) r mr =28 w ; i mr = 10 ma; t amb =25 c; no lead inductance -- 400 khz b f(h) upper noise band edge (+3 db) r mr =28 w ; i mr = 10 ma; t amb =25 c; no lead inductance - 220 - mhz a cs channel separation; note 4 unselected head - 50 - db psrr power supply rejection ratio; note 5 f < 1 mhz; i mr =10ma - 80 - db f < 100 mhz; i mr =10ma - 50 - db cmrr common mode rejection ratio; note 5 from nrx-nry to rdx-rdy r mr mismatch < 5% i mr =10ma f < 1 mhz - 45 - db f < 100 mhz - 25 - db
1997 apr 08 19 philips semiconductors preliminary speci?cation pre-ampli?er for hard disk drive (hdd) with mr-read/inductive write heads tda5155 dr rejection ratio of sclk and sdata; note 6 from sclk, sdata inputs to the rdx-rdy outputs; a 200 mv (peak-to-peak) signal is applied to sclk or sdata inputs at 25 mhz, and measurement is performed at rdx-rdy - 50 - db v o(r)(dif) output dc offset voltage in read mode (differential after dc settling) dc voltage between rdx and rdy -- 0.2 v z o(r) output impedance in read mode single ended - 16 -w i o(max)(dif) maximum differential output current - 4 - ma v o(cm) common mode output voltage in read mode rdx, rdy 1.0 1.5 2.0 v common mode dc supply rejection ratio in read mode - 20 - db z o(n)(dif) differential output impedance in other modes (write, standby, sleep) - 50 - k w write characteristics i wr write current adjust range (in the write drivers) r ext =10k w ; 1 ma steps 20 35 51 ma d i wr tolerance (excluding r ext )i wr programmed at 35 ma - 7 - % v s(max)(p-p) maximum voltage swing (peak-to-peak value) v cc(wd) =5v -- 8v v cc(wd) = 8 v (differential) -- 13 v r o(dif) differential output resistance - 200 -w c o(dif) differential output capacitance not including the head capacitance - 5 - pf t r ,t f write current rise/fall time without ?ip-?op (10% to 90%); note 7 l h = 150 nh; r h =10 w; i wr = 35 ma; f = 20 mhz v cc(wd) = 8.0 v -- 1.8 ns v cc(wd) = 6.5 v -- 2.1 ns t as write current rise/fall time asymmetry; note 8 percentage of t r or t f (t r or t f and logic asymmetry) -- 5% t pd propagation delay 50% of (wdix/wdiy) to 50% of (wx, wy) write head short-circuited, data ?ip-?op by-passed -- 5ns a cs channel separation not-selected head - 45 - db symbol parameter conditions min. typ. max. unit v d ocm () v cc d --------------------- -
1997 apr 08 20 philips semiconductors preliminary speci?cation pre-ampli?er for hard disk drive (hdd) with mr-read/inductive write heads tda5155 switching characteristics f sclk serial interface clock rate -- 25 mhz d v o(cm) common mode dc output voltage change from read to write mode i mr = 10 ma; i wr =35ma - 200 - mv t rec(w-r) write-to-read recovery time (ac and dc settling); note 9 from 50% of the rising edge of r/ w to steady state read-back signal: ac and dc settling at 90% (without load at rdx, rdy) read amplifier off: d5 = 0 - 3 4.5 m s read amplifier on: d5 = 1 - 100 150 ns t sw(r) head switching (in read mode), standby to read active and mr current change recovery time. (ac and dc settling); note 10 from falling edge of sen to steady state read-back signal (without load at rdx, rdy) - 3 4.5 m s t off(r) read ampli?er off time from falling edge of r/ w to read head inactive -- 50 ns t st(w) write settling times; note 11 from 50% of the falling edge of r/ w to 90% of the steady state write current (in write mode) -- 70 ns t off(w) write ampli?er off time from rising edge of r/ w to 1 10 i wr (programmed) (i wr =35ma) -- 50 ns t sw(w) head switching (in write mode), and standby to write head active from falling edge of sen to write head active - 50 70 ns t sw(s) switch time to and from sleep mode -- 100 m s dc characteristics i cc(r) read mode supply current i mr = 10 ma; note 12 - 72 80 ma i cc(w) write mode supply current i wr = 35 ma; note 13 from v cc (5 v) - 33 41 ma from v cc(wd) (5 to 8 v) - 54 61 ma i dd(stb) standby mode supply current - 0.25 1 ma i dd(s) sleep mode supply current static -- 0.02 - ma v ref reference voltage for r ext - 1.32 - v symbol parameter conditions min. typ. max. unit
1997 apr 08 21 philips semiconductors preliminary speci?cation pre-ampli?er for hard disk drive (hdd) with mr-read/inductive write heads tda5155 notes to the characteristics 1. the differential voltage gain depends on the mr resistance. it can be improved by programming the d4 bit in the configuration register. 2. the gain boost implements a pole-zero combination: the +3 db gain boost corner frequency is . the - 3 db gain attenuation corner frequency is , where d3, d2, d1 and d0 are to be programmed via the serial interface. in practical use, the bandwidth is limited by the inductance of the connection between the mr heads and the pre-amplifier. 3. noise calculation a) definitions: the amplifier has a low input resistance. no lead resistance is taken into account. the input referred noise voltage, excluding the noise of the mr resistors, is defined as: , where g v is the voltage gain, v no is the noise voltage at the output of the amplifier, k is the boltzmann constant and t is the temperature in k. the noise figure is defined as follows: in 1 hz bandwidth. note that r mr includes all resistances between rx or ry to ground. b) noise figure versus i mr and r mr : table 1 shows the variation of the noise figure with i mr and r mr . c) input referred noise voltage: the input referred noise voltage calculation can be significantly different (from 1.0 to 0.44 nv/ ? hz for instance) by taking an equivalent signal-to-noise ratio into account when using two mr stripes (28 w for each stripe) or one mr stripe (42 w ). it assumes that the signal coming from the head is larger for a dual-stripe head than for a single-stripe head (50% extra signal for a dual-stripe head). 4. the channel separation is defined by the ratio of the gain response of the amplifier using the selected head h(n) to the gain response of the amplifier using the adjacent head h(n 1), head h(n) being selected. 800 mhz 8.d3 4.d2 2.d1 1.d0 +++ --------------------------------------------------------------------- 800 mhz 8.d3 4.d2 2.d1 1.d0 +++ --------------------------------------------------------------------- v irn () 2 v no g v --------- 2 4kt r mr1 r mr2 + () C = f10 v no g v --------- 2 4kt r mr1 r mr2 + () ----------------------------------------------------------- - ? ? ? ? ? ?? log = 5. the psrr (in db) is defined as input referred ratio: , where g v is the differential input to differential output gain, and g p is the power supply to differential output gain.the cmrr (in db) is defined as input referred ratio: , where g v is the differential input to differential output gain and g cm is the common mode input to differential output gain. flex and board lay-out may affect these parameters significantly. 6. this refers to the crosstalk from sclk and sdata inputs via the read inputs to rdx and rdy. two cases can be distinguished: a) when sen is low, sclk and sdata are prohibited reaching the device and crosstalk is low. b) programming via the serial interface is done with sen high. then crosstalk can occur. a careful design of the board or flex-foil is required to avoid crosstalk via this path. 7. the rise and fall times depend on the write amplifier/write head combination. l h and r h represent the components on the evaluation board. parasitic capacitances also limit the performance. 8. the write current rise/fall time asymmetry is defined by 9. write-to-read recovery time includes the write mode to read mode switching using the r/ w pin on the same head (see fig.5). the ac signal reaches its full amplitude few tens of ns after appearing at the reader rdx and rdy outputs. 10. in read mode, the head switching, standby to read active switching and changing mr current include fast current settling (see fig.5). the ac signal reaches its full amplitude few tenth of ns after appearing at the reader rdx and rdy outputs. 11. write settling time includes the read mode to write mode switching using the r/ w pin. 12. the typical supply current in read mode depends on the bias current for the mr element. 13. the typical supply current in write mode also depends on the write current. psrr 20 log g v g p ------ - = cmrr 20 log g v g cm ---------- - = t r t f C 2t r t f + () -----------------------
1997 apr 08 22 philips semiconductors preliminary speci?cation pre-ampli?er for hard disk drive (hdd) with mr-read/inductive write heads tda5155 table 1 noise ?gure r mr ( w ) f (db) i mr = 7 ma i mr =10ma i mr =15ma 20 2.7 2.9 3.1 25 2.8 3.0 3.3 30 2.9 3.1 3.5 fig.5 timing diagram of the reader: write-to-read switching on the same logic head. handbook, full pagewidth mgg985 t off(r) t rec(w-r) rdx-rdy r/w fig.6 timing diagram of the reader: typical head, current and standby-to-read characteristics. handbook, full pagewidth mgg986 t sw(r) rdx-rdy sen
1997 apr 08 23 philips semiconductors preliminary speci?cation pre-ampli?er for hard disk drive (hdd) with mr-read/inductive write heads tda5155 14 definitions 15 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
internet: http://www.semiconductors.philips.com philips semiconductors C a worldwide company ? philips electronics n.v. 1997 sca54 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. +31 40 27 82785, fax. +31 40 27 88399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. +64 9 849 4160, fax. +64 9 849 7811 norway: box 1, manglerud 0612, oslo, tel. +47 22 74 8000, fax. +47 22 74 8341 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. +63 2 816 6380, fax. +63 2 817 3474 poland: ul. lukiska 10, pl 04-123 warszawa, tel. +48 22 612 2831, fax. +48 22 612 2327 portugal: see spain romania: see italy russia: philips russia, ul. usatcheva 35a, 119048 moscow, tel. +7 095 755 6918, fax. +7 095 755 6919 singapore: lorong 1, toa payoh, singapore 1231, tel. +65 350 2538, fax. +65 251 6500 slovakia: see austria slovenia: see italy south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430 johannesburg 2000, tel. +27 11 470 5911, fax. +27 11 470 5494 south america: rua do rocio 220, 5th floor, suite 51, 04552-903 s?o paulo, s?o paulo - sp, brazil, tel. +55 11 821 2333, fax. +55 11 829 1849 spain: balmes 22, 08007 barcelona, tel. +34 3 301 6312, fax. +34 3 301 4107 sweden: kottbygatan 7, akalla, s-16485 stockholm, tel. +46 8 632 2000, fax. +46 8 632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. +41 1 488 2686, fax. +41 1 481 7730 taiwan: philips semiconductors, 6f, no. 96, chien kuo n. rd., sec. 1, taipei, taiwan tel. +886 2 2134 2865, fax. +886 2 2134 2874 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, tel. +66 2 745 4090, fax. +66 2 398 0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. +90 212 279 2770, fax. +90 212 282 6707 ukraine : philips ukraine, 4 patrice lumumba str., building b, floor 7, 252042 kiev, tel. +380 44 264 2776, fax. +380 44 268 0461 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. +44 181 730 5000, fax. +44 181 754 8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. +1 800 234 7381 uruguay: see south america vietnam: see singapore yugoslavia: philips, trg n. pasica 5/v, 11000 beograd, tel. +381 11 625 344, fax.+381 11 635 777 for all other countries apply to: philips semiconductors, marketing & sales communications, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, fax. +31 40 27 24825 argentina: see south america australia: 34 waterloo road, north ryde, nsw 2113, tel. +61 2 9805 4455, fax. +61 2 9805 4466 austria: computerstr. 6, a-1101 wien, p.o. box 213, tel. +43 1 60 101, fax. +43 1 60 101 1210 belarus: hotel minsk business center, bld. 3, r. 1211, volodarski str. 6, 220050 minsk, tel. +375 172 200 733, fax. +375 172 200 773 belgium: see the netherlands brazil: see south america bulgaria: philips bulgaria ltd., energoproject, 15th floor, 51 james bourchier blvd., 1407 sofia, tel. +359 2 689 211, fax. +359 2 689 102 canada: philips semiconductors/components, tel. +1 800 234 7381 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. +852 2319 7888, fax. +852 2319 7700 colombia: see south america czech republic: see austria denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. +45 32 88 2636, fax. +45 31 57 0044 finland: sinikalliontie 3, fin-02630 espoo, tel. +358 9 615800, fax. +358 9 61580920 france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. +33 1 40 99 6161, fax. +33 1 40 99 6427 germany: hammerbrookstra?e 69, d-20097 hamburg, tel. +49 40 23 53 60, fax. +49 40 23 536 300 greece: no. 15, 25th march street, gr 17778 tavros/athens, tel. +30 1 4894 339/239, fax. +30 1 4814 240 hungary: see austria india: philips india ltd, shivsagar estate, a block, dr. annie besant rd. worli, mumbai 400 018, tel. +91 22 4938 541, fax. +91 22 4938 722 indonesia: see singapore ireland: newstead, clonskeagh, dublin 14, tel. +353 1 7640 000, fax. +353 1 7640 200 israel: rapac electronics, 7 kehilat saloniki st, po box 18053, tel aviv 61180, tel. +972 3 645 0444, fax. +972 3 649 1007 italy: philips semiconductors, piazza iv novembre 3, 20124 milano, tel. +39 2 6752 2531, fax. +39 2 6752 2557 japan: philips bldg 13-37, kohnan 2-chome, minato-ku, tokyo 108, tel. +81 3 3740 5130, fax. +81 3 3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. +82 2 709 1412, fax. +82 2 709 1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. +60 3 750 5214, fax. +60 3 757 4880 mexico: 5900 gateway east, suite 200, el paso, texas 79905, tel. +9-5 800 234 7381 middle east: see italy printed in the netherlands 297027/20/01/pp24 date of release: 1997 apr 08 document order number: 9397 750 01427

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